Category

Digital Logic & Computer Architecture

Boolean logic, computer organization, encoding, memory behavior, and processor timing tools.

Live

IEEE-754 Visualizer

Convert decimal values into 32-bit float fields.

Live

4-Variable K-Map Solver

Simplify SOP expressions from a clickable K-map.

Planned

5-Variable K-Map Solver

Step up to larger Karnaugh-map reductions.

Planned

Logic Gate Simulator

Drag and drop gates to generate truth-table behavior.

Planned

Hamming Code Generator/Error Corrector

Simulate ECC parity generation and single-bit correction.

Planned

CRC-32 / CRC-16 Checksum Calculator

Calculate checksums for protocol and storage payloads.

Planned

Instruction Cycle Time Calculator

Input CPI and clock speed to estimate execution time.

Planned

Cache Hit/Miss Ratio Simulator

Visualize direct-mapped and set-associative cache behavior.

Live

Gray Code to Binary Converter

Translate Gray-code sequences into ordinary binary.

Planned

Priority Encoder Simulator

Inspect encoder outputs for competing input priorities.

Planned

7-Segment Display Hex Decoder

Show which display segments illuminate for each hex digit.

Planned

ALU Operation Simulator

Visualize add, subtract, AND, and OR at the bit level.

Planned

Barrel Shifter Visualizer

Inspect rotate and shift operations across a word.

Planned

Two's Complement Overflow Detector

Detect signed overflow conditions for binary arithmetic.

Planned

Finite State Machine Verilog Generator

Draft Verilog state-machine scaffolds from state definitions.

Planned

Booth's Multiplication Algorithm Step-Through

Walk through signed binary multiplication steps.

Planned

Pipeline Stalls/Hazards Visualizer

See how structural, data, and control hazards affect a pipeline.